This invention relates to integrated circuits, and more particularly, to integrated circuits with input voltage clamping circuits.
As integrated circuits scale towards smaller technology nodes (i.e., 20 nanometers and beyond), the maximum nominal voltage that can be handled by thick gate input/output (IO) transistors becomes smaller. For example, the nominal power supply voltage that is used to power a thick gate IO transistor might be limited to 1.8 V. However, input signals that are received at the IO pads can exhibit voltage swings of up to 3 V or more to allow for backward compatibility with legacy interface protocols. These input signals are typically received at an input voltage clamp that is configured to shift down the high voltage level at the IO pad down to the lower nominal voltage.
A conventional input voltage clamp consists of a single n-channel metal-oxide-semiconductor (NMOS) pass gate transistor. The NMOS transistor has a drain terminal that receives the input signal from the IO pad, a source terminal that is connected to a corresponding receiver in the integrated circuit, and a gate terminal that is biased to the nominal voltage level. Connected in this way, the input signal will have its voltage swing clipped down from the higher IO voltage level to less than the lower nominal voltage level.
Such types of conventional voltage clamp often suffer from loss of a substantial portion of the input signal when passing through the NMOS pass gate. The input signal is an analog signal having a slew rate that is critical to determining the duty cycle of the receiver output. In scenarios where a 3.3 V IO signal is shifted down to a 1.8 V, 1.5 V, or 1.1 V receiver input voltage level, up to two-thirds or more of the input signal can be lost, which can severely impact performance of the receiver subsystem.